Equalizer filter with mismatch tolerant detection mechanism for lower and higher frequency gain loops

ABSTRACT

The present invention provides an equalizer filter for compensating a received distorted signal for frequency dependent signal modifications introduced by a transmission channel. The equalizer filter comprises at least one compensation stage. A compensation stage has at least one gain parameter. Different compensation stages may have different gain parameters. The equalizer filter according to embodiments of the present invention comprise at least one switch, the at least one switch being for changing at least one of the gain parameters in time in function of the compensated signal. In embodiments of the present invention, for every gain parameter a switch may be present in the equalizer filter.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to the field of data communication. Moreparticularly, the present invention relates to devices and correspondingmethods for equalizer filtering in a line equalizer system, whichrestore attenuated signals transmitted over a communication ortransmission channel for a wide variety of communication or transmissionchannels with an acceptable amount of jitter. The present invention alsorelates to the use of an equaliser in communications system, e.g. in amodem.

BACKGROUND OF THE INVENTION

An equalizer system in general compensates frequency dependent lossesthat a signal experiences when passing through a transmission channel.Transmission channels include, but are not limited to, a wire, a pair ofwires, an optical fibre, the reading and writing channels of a storagedevice like a hard-disc or optical disc, a wireless connection such as apoint-to-point or diffuse infra-red or radio connection. A pair of wiresincludes a twisted pair, a twinax coax or a differential transmissionline on a printed circuit board.

The compensation level of an equalizer system in general can beself-adaptive, fixed or programmable e.g. by a voltage or via a set ofswitches. A self-adaptive equalizer system continuously estimates thematching compensation level. It typically includes an adaptable filter,a control loop and an output reconstruction unit.

EP-1392001 describes how to organise a control loop in an equalizersystem such that self-adaptation is achieved, independently from thetransmit amplitude and the transmitted bit pattern. A feed-back controlsignal is generated from the equalised output of an equalizer filter.Depending on whether the output signal has been under- orover-compensated, the feed-back control signal increases or decreases,such that after a reasonable time the feed-back control signal convergesto a value where matched compensation is reached. The control loop isformed by a first means for measuring a short-term-amplitude signal ofthe output signal, a second means for measuring a long-term-amplitudesignal of the output signal and a comparator means for comparing theshort-term-amplitude signal and the long-term-amplitude signal, and fordetermining the evolution of the feed-back control signal.

U.S. Pat. No. 7,180,941 discloses a way to regulate low and highfrequency components by comparing low and high frequency components inthe signals before and after a slicer digitizer circuit.

EP-1763188 also uses low pass and high pass filtering in its low- andhigh frequency gain regulation systems with increased precision due to acomparator current being adapted in time.

The above documents describe detectors for tuning low and high frequencygain that are using filters based on classical first and/or second orderfilters. When not using large chip-scale inductors these filtersinevitably reduce signal amplitudes. These reduced signal amplitudes arethen to be compared making the detection susceptible to mismatches inused comparator circuits.

SUMMARY OF THE INVENTION

The teachings of the present invention permits the design of improvedequalizer filters and equalizer filtering methods for use in single ormultistage equalizer systems which provide restoration of data signalstransmitted over a communication channel showing high-frequencyattenuation behaviour, high-frequency being defined with respect to thedata rate of the transmitted signals. More in particular, structures andmethods are provided that allow good detection mechanisms for lower andhigher frequency gain loops that are very tolerant for transistormismatches in the equalizer circuits.

Allowing mismatches in pairs of transistors in an equalizer circuit isimportant when aiming at high-speed operation.

Further, when aiming at low-voltage equalizers, given transistormismatch voltages become relatively more important since inevitably onewill have to work with smaller internal high-speed data signals. In thiscase, a higher tolerance to transistor mismatches increases theproduction yield significantly. Finally, combined high-speed andlow-voltage operation is what many equalizers require in present day andfuture CMOS technologies, thereby operating at voltages smaller than—orequal to—1.2V and at high speed bit rates, i.e. at 100 Mbps to 100 Gbps.

In a first aspect, the present invention provides an equalizer filter,more particularly an adaptive equalizer filter, for compensating areceived distorted or dispersive signal for frequency dependent signalmodifications introduced by a transmission channel. The equalizer filtermay be a single stage or multi-stage filter, i.e. it may comprise atleast one compensation stage. A compensation stage has at least one gainparameter. Different compensation stages may have different gainparameters, e.g. one compensation stage may be tunable in high frequencywhile another compensation stage may be tunable in low frequency. Theequalizer filter according to embodiments of the first aspect of thepresent invention may comprise at least one switch, the at least oneswitch being for changing at least one of the gain parameters in time infunction of the compensated signal. In embodiments of the presentinvention, for every gain parameter a switch may be present in theequalizer filter.

An equalizer filter according to embodiments of the present inventionmay furthermore comprise a control circuit for controlling the actuationof the at least one switch so as to control when the at least one gainparameter is changed.

An equalizer filter according to embodiments of the present inventionmay furthermore comprise storage means for storing the gain parameters.The storage means may for example be a capacitor, e.g. a parasiticcapacitance.

An equalizer filter according to embodiments of the present inventionmay furthermore comprise a detection circuit for detecting from thecompensated signal mismatches in at least one of the gain parameters,and for generating a corresponding mismatch detection signal. Themismatch detection signal may instantaneously indicate a requiredincrease or decrease of at least one of the gain parameters.

In an equalizer filter according to embodiments of the presentinvention, the at least one switch may be adapted to signal through orlink through the mismatch detection signal, more particularly forexample to a gain parameter storage means, thus updating the at leastone gain parameter with the required increase or decrease. Thesignalling through may be a combination of multiplexing in time and lowpass filtering.

The detection circuit may be a rectifying comparator circuit.

The detection circuit may comprise two differential inputs. Eachdifferential input may comprise two input nodes. The detection circuitmay be adapted to compare, from each differential input, signals onthose input nodes which are highest in voltage.

The detection circuit may comprise a comparator.

The detection circuit may be adapted for comparing input and outputsignals of a limiting amplifier.

The detection circuit may furthermore comprise at least one rectifier.

In a second aspect, the present invention provides an equalizer filter,more particularly an adaptive equalizer filter, for compensating areceived distorted or dispersive signal for frequency dependent signalmodifications introduced by a transmission channel. The equalizer filteraccording to embodiments of the present invention comprises at least onecompensation stage. There are at least two gain parameters for thecompensation stages, and each compensation stage has at least one gainparameter. The equalizer filter according to embodiments of the presentinvention comprises a gain parameter updating circuit for updating theat least two gain parameters, and a detection circuit for detecting,from the compensated signal, mismatches in the gain parameters. Thedetection circuit may be adapted for generating a mismatch detectionsignal, the mismatch detection signal being common for the at least twogain parameters.

It is an advantage of embodiments of the present invention that, due tothe detection signal being common for the at least two gain parameters,potential offsets, which may be introduced on the gain parameters e.g.by amplifying signals, are introduced equally for all gain parameters tobe changed.

In an equalizer filter according embodiments of the present invention,the mismatch detection signal may instantaneously indicate a requiredincrease or decrease of the gain parameters.

In an equalizer filter according to embodiments of the presentinvention, the detection circuit may comprise two differential inputs.Each differential input may comprise two input nodes, and the detectioncircuit may be adapted to compare, from each differential input, signalson those input nodes which are highest in voltage.

In an equalizer filter according to embodiments of the presentinvention, the detection circuit may furthermore comprise at least onerectifier for rectifying signals on the differential inputs.

The detection circuit may comprise a comparator for comparing signals onthe differential inputs.

The detection circuit may be adapted for comparing input and outputsignals of a limiting amplifier.

An equalizer filter according to embodiments of the present inventionmay furthermore comprise at least one switch, the at least one switchbeing for changing at least one of the gain parameters in time infunction of the compensated signal. The at least one switch may beadapted to signal through or link through the mismatch detection signalfor updating the at least one gain parameter with the required increaseor decrease.

In a third aspect, the present invention provides an equalizer systemfor compensating a received distorted signal for frequency dependentsignal modifications introduced by a transmission channel. The equalizersystem according to the third aspect comprises an equalizer filteraccording to any of the embodiments of the equalizer filters of thefirst or second aspects of the present invention.

In a fourth aspect, the present invention provides a method forcompensating a distorted signal for frequency dependent signalmodifications introduced by a transmission channel, the signal having anamplitude. The method comprises receiving a distorted signal, providingat least two gain parameters and compensating said distorted signal byamplifying the received signal in at least one amplifying compensationstage using the provided gain parameters, and outputting a compensatedsignal. The method according to embodiments of the present inventionfurthermore comprises, in function of the amplitude of the compensatedsignal, changing at least one of the gain parameters multiplexed intime. A plurality of gain parameters may be provided to the at least oneat least one compensating stage, and each of the plurality of gainparameters may be changed multiplexed in time, e.g. they may be changedone after the other. In alternative embodiments, at least one of thegain parameters may be changed continuously, depending on the amplitudeof the compensated signal, and at least another one of the gainparameters may be changed intermittently, multiplexed in time.

Changing the gain parameters may comprise generating a mismatchdetection signal from the compensated signal and multiplexing thatmismatch detection signal in time for adapting at least one of the gainparameters. The mismatch detection signal may instantaneously indicate arequired increase or decrease of at least one of the gain parameters.

Generating a mismatch detection signal may comprise comparing thecompensated signal with an amplified and/or saturated version of thecompensated signal.

A method according to embodiments of the present invention mayfurthermore comprise using the mismatch detection signal for changing atleast one of the gain parameters. Changing the gain parameters maycomprise multiplexing at least one switch in time, for multiplexedsignalling through the mismatch detection signal to at least one of thegain parameters.

A method according to embodiments of the present invention mayfurthermore comprise storing the at least two gain parameters in amemory element, e.g. a capacitor, such as for example a parasiticcapacitance.

In a fifth aspect, the present invention provides a method forcompensating a distorted signal for frequency dependent signalmodifications introduced by a transmission channel, the signal having anamplitude. The method comprises receiving a distorted signal, providingat least two gain parameters and compensating said distorted signal byamplifying the received signal in at least one amplifying compensationstage using the provided gain parameters, outputting a compensatedsignal, and detecting from the compensated signal, mismatches in thegain parameters and updating the at least two gain parameters. Detectingmismatches in the gain parameters may be adapted in accordance withembodiments of the present invention for generating a mismatch detectionsignal common for the at least two gain parameters.

Updating the at least two gain parameters may comprise supplying thecommon detection signal to each of the at least two gain parameters, andmultiplexing it in time for at least one of the gain parameters, i.e.applying or not applying it in time, so as to changing the gainparameters in time in function of the compensated signal. Updating theat least two gain parameters may comprise multiplexing the commondetection signal between the at least two gain parameters.

The mismatch detection signal may instantaneously indicate a requiredincrease or decrease of at least one of the gain parameters. Updatingthe at least two gain parameters may comprise signalling through themismatch detection signal for updating the gain parameters with therequired increase or decrease.

These and other characteristics, features and advantages of the presentinvention will become apparent from the following detailed description,taken in conjunction with the accompanying drawings, which illustrate,by way of example, the principles of the invention. This description isgiven for the sake of example only, without limiting the scope of theinvention. The reference figures quoted below refer to the attacheddrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic representation of an adaptive equalizer withdetection and updating mechanism for gain parameters HFgain and LFgainaccording to embodiments of the present invention.

FIG. 2 shows the connect signals connect_LF and connect_HF in responseto zero-crossings of a differential input signal “In1-In2” versus time,the connect signals connect_LF and connect_HF controlling switches forchanging the gain parameters HFgain and LFgain according to embodimentsof the present invention.

FIG. 3 shows an example of an implementation of the connect controlblock of FIG. 1 for generation of the signals connect_LF and connect_HF.

FIG. 4 shows an implementation of the rectifying comparator mechanism ofFIG. 1 in the form of a rectifying comparator grouped in one circuitfeaturing also AC-coupling, in accordance with embodiments of thepresent invention.

FIG. 5 shows signal curves of a simulation of an adaptive equalizercircuit according to embodiments of the present invention.

FIG. 6 shows a schematic representation of an adaptive equalizeraccording to embodiments of the present invention, having same elementsas the adaptive equalizer of FIG. 1, however, further including extraamplification means located in the gain updating circuit after theswitches.

FIG. 7 shows a schematic representation of an adaptive equalizeraccording to embodiments of the present invention, regulating High,Middle, and Low frequency gain separately.

FIG. 8 shows a schematic representation of connect signals to begenerated by the connect control block in the case of the adaptiveequalizer schematically illustrated in FIG. 7.

FIG. 9 shows a schematic representation of an adaptive equalizer withdetection and updating mechanism for gain parameters HFgain and LFgainaccording to alternative embodiments of the present invention.

In the different figures, the same reference signs refer to the same oranalogous elements.

DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The present invention will be described with respect to particularembodiments and with reference to certain drawings but the invention isnot limited thereto but only by the claims. The drawings described areonly schematic and are non-limiting. In the drawings, the size of someof the elements may be exaggerated and not drawn on scale forillustrative purposes. The dimensions and the relative dimensions do notcorrespond to actual reductions to practice of the invention.

It is to be noticed that the term “comprising”, used in the claims,should not be interpreted as being restricted to the means listedthereafter. Thus, the scope of the expression “a device comprising meansA and B” should not be limited to devices consisting only of componentsA and B. It means that with respect to the present invention, the onlyrelevant components of the device are A and B.

Similarly, it is to be noticed that the term “coupled” should not beinterpreted as being restricted to direct connections only. Thus, thescope of the expression “a device A coupled to a device B” should not belimited to devices or systems wherein an output of device A is directlyconnected to an input of device. B. It means that there exists a pathbetween an output of A and an input of B which may be a path includingother devices or means.

The invention will be described by a detailed description of severalembodiments of the invention. It is obvious that other embodiments ofthe invention can be configured by a person skilled in the art withoutdeparting form the true spirit or technical teaching of the invention,the invention therefore being limited only by the terms of the appendedclaims. It will be clear for a person skilled in the art that thepresent invention is also applicable to similar circuits that can beconfigured in any transistor technology, including for example, but notlimited thereto, CMOS, BICMOS and SiGe BICMOS. It will furthermore beclear that similar merits of the invention can be obtained whensingle-ended signals are implemented as differential signals andvice-versa, without departing from the true spirit of the invention.

FIG. 1 shows a multiple stage example of an adaptive equalizer accordingto embodiments of the present invention. The adaptive equalizer may beused in a suitable electronic device, e.g. in a modem or receiver of atelecommunications device.

The adaptive equalizer 41 according to embodiments of the presentinvention shows at least one amplifying compensation stage. In theembodiment illustrated in FIG. 1, the adaptive equalizer 41 shows acascade of amplifying compensation stages coupled in series, moreparticularly a cascade of four compensation stages 43, 44, 45, 46. Thenumber of amplifying compensation stages according to embodiments of thepresent invention can also be less or more than four. The number ofamplifying compensation stages depends on the wanted or required totalcompensation to be reached, and can differ from application toapplication. This number also depends on the used circuit integrationtechnology. Therefore, although by way of example an adaptive equalizer41 is shown having four amplifying compensation stages 43, 44, 45, 46,the invention is not limited thereto.

The signal to be recovered enters at the input of the first amplifyingcompensation stage 43, at the input node comprising input terminals inA,inB. Typically, a signal is supplied to the input node of the equalizer41 that has more or less suffered from frequency attenuation from atransmission channel with limited bandwidth characteristics, wherebyhigher frequencies are more attenuated than lower frequencies. The inputsignal is input in the equalizer 41 at the input node, which serves asthe differential input node of the amplifying compensation stage 43.Amplifying compensation stages 43, 44, 45, 46 are used to make an “asgood as possible” digital data stream at the output node of the lastamplifying compensation stage 46, also the entrance of the limitingamplifier 47, by analog inverse filtering. The amplifying compensationstages 43, 44, 45, 46 can be any type of suitable compensation stages,e.g. compensation stages with a fixed higher frequency gaincompensation, programmable compensation stages, tunable compensationstages. Examples of amplifying compensation stages, and how they aredriven can be found in literature by the person skilled in the art,including in WO 2004/73274, EP-1622285, EP-1763188. Such stages can betuned sequentially, or in parallel. For some applications and dependingon the bit rate of the envisaged equalizer it can also be sufficient towork with a single stage.

After having traveled through the compensation stages 43, 44, 45, 46,the signal arrives at the limiting amplifier 47 for amplifying and/ordigitizing the output of the last amplifying compensation stage 46. Thislimiting amplifier 47 may itself have a fixed maximum output amplitude.

After the limiting amplifier 47, an output circuit 48 is provided.Output circuit 48 has an output node comprising differential outputterminals outA, outB, and can include any useful stage following anequalizing filter in an equalizer system, including but not limited to abit-slicer, a limiting amplifier, a DC-restoring system or aSchmitt-trigger, and possibly an output driver stage, all known by aperson skilled in the art. The output circuit 48 together with theequalizer 41 are part of an equalizer system. This output circuit 48 maybe provided to compensate amplitude variations obtained by equalizing,at the expense of very little or no additional jitter.

To obtain an equalizer 41 that is robust to transmit amplitudevariations, the amplifying compensation stages 43, 44, 45, 46 preferablyeach have at least one gain parameter that tunes the low frequency gain,and another gain parameter that tunes the high frequency gain. In FIG.1, these gain parameter values are stored as a voltage on the nodesHFgain for the high frequency gain level, and on node LFgain, for thelow frequency gain level. It is assumed hereby that a higher storedvoltage corresponds to a higher gain value, in both cases. Typical gainranges for commercial equalizers are from −5 dB to +10 dB for the lowfrequency gain range, and −5 dB to +35 dB for the high frequency gainrange. At the output of the last amplifying compensation stage 46 in thecascade, the signal is in its differential form between nodes preA andpreB.

This signal enters the limiting amplifier 47 where it is amplified by apre-defined amplification factor over the full useful frequency band,e.g. by 4 to 6 dB. The limiting amplifier 47 has a limited capability ofamplification: there is a limitation to the output amplitude, e.g. to250 mV for a 1V technology, or to 700 mV for a 3.3V chip technology.This limiting amplifier 47 can be a current mode logic stage (CML-stage)whereby this limitation of the output amplitude gives a digitizingbehaviour when the input waveform itself had already a large enoughamplitude. Due to its limited output amplitude, possible overshootspresent at the input of the limiting amplifier 47 will be clipped in theoutput signal when these overshoots would be too large to beaccommodated by the limiting amplifier 47. It is advised to use a singlestage limiting amplifier 47 for good operation of embodiments of thepresent invention, although the present invention is not limitedthereto. The output signal of the limiting amplifier 47 is presentbetween the nodes postA and postB. This signal may be further amplified,and brought to a node with lower impedance than any previous node in thesignal path, in order to form the digital output of the equalizer 41.The bringing to a node with lower impedance may be done to match theimpedance of attached transmission lines. An output driver may typicallybe needed in the output circuit 48 for driving low impedancetransmission lines.

The at least one gain parameter is changed, in accordance withembodiments of the present invention, in function of the compensatedsignal at the output nodes preA, preB of the last compensation stage 46and optionally in function of the signal at the output nodes postA,postB of the limiting amplifier stage 47. If the compensated signalamplitude is too high, the gain parameters will be lowered, and if thecompensated signal amplitude is too low, the gain parameters will beraised correspondingly.

In order to determine the change of the gain parameters, a detectionmechanism 42 for determining the required high frequency gain and lowfrequency gain is provided in accordance with embodiments of the presentinvention. The detection mechanism 42 may be a rectifying comparatormechanism. In the embodiment of the present invention illustrated inFIG. 1, the signals on the input nodes preA, preB of the limitingamplifier 47 are rectified in a first rectifier 30. The signals on theoutput nodes postA, postB of the limiting amplifier 47 are rectified bya second rectifier 31. The output signals of the first and secondrectifiers 30, 31 are compared by a comparator 32. It is advantageous ifthe comparator 32 and its preceding first and second rectifiers 30, 31have a sufficiently high bandwidth, comparable to the maximum bit-rate.For example, a 10-Gbps equalizer 41 would preferably have 10-GHz fastrectifiers 30, 31 and comparator 32. In that way, the voltage on theoutput node adjust_gain of the comparator 32, will always andinstantaneously tell whether the absolute value of the signal at theinput of the limiting amplifier 47 is smaller or larger than theabsolute value at the output of the equalizer 41. When the voltage onthe output node adjust_gain of the comparator 32 is HIGH, this indicatesthat the absolute value of the signal at the input of the limitingamplifier 47 is too low and should be higher in order to match theabsolute value of the signal at the output of the limiting amplifier 47.When the voltage on the output node adjust_gain of the comparator 32 isLOW, this indicates that the absolute value of the signal at the inputof the limiting amplifier 47 is too high and should be lower in order tomatch the absolute value of the signal at the output of the limitingamplifier 47. The gain parameters of the compensation stages 43, 44, 45,46 may be controlled to be adapted accordingly.

The control of the gain parameters is performed in updating mechanism 40as follows. During a pre-determined period after a zero-crossing of thedata, e.g. on the node preA, preB, the signal on the output nodeadjust_gain of the detection circuit 42, in the embodiment illustratedin FIG. 1 the output of comparator 32, is indicative for whether thereis too much or too little high frequency gain. Just before azero-crossing the signal on the output node adjust_gain of the detectioncircuit 42, in the embodiment illustrated in FIG. 1 the output ofcomparator 32, is indicative for whether there is too much or too littlelow frequency gain. Now, in order to adapt the voltages on the HFgainand LFgain nodes to this fact, the updating circuit 40 comprises aconnect control block 33, to control the enable of first and secondswitches 34, 35 to link through the signal on the output nodeadjust_gain of the comparator 32 to the HFgain node and LFgain node,respectively, at the appropriate moments in time, and to update theHFgain and LFgain voltages (gain parameters) in the right direction (upor down). This way, the signal on the output node adjust_gain of thedetection circuit 42, e.g. at the output node of comparator 32, is timemultiplexed in order to separately control the high frequency gainparameter (HFgain) and the low frequency gain parameter (LFgain).

The connect control block 33 generates the enable signals connect_HF andconnect_LF for first and second switches 34, 35, based on the values ofthe compensated signal at the output nodes preA, preB of the lastcompensation stage 46. This is illustrated in FIG. 2. In between twozero-crossings of a data signal at the output nodes of the amplifyingcompensation stages, the time domain is split into different parts, eachpart being for updating a particular gain parameter. One implementationembodiment of a method for controlling adaptation of the gain parametervalues on the HFgain and LFgain nodes is to choose a fixed period forkeeping the first switch 34 (for controlling the high frequency gainparameter value) conductive after a zero-crossing of the data signal 50at the output of the compensation stages, in particular at the output ofthe last compensation stage 46. This period is called the “just-crossedperiod” 53. This just-crossed period 53 can be for example for a periodof 1 bit. At 1-Gbps this just-crossed period 53 then corresponds to1-ns. During the just-crossed period 53, the connect_HF signal 51 isHIGH. The remainder of the time until the next zero crossing can then beused for making the second switch 35 (for controlling the low frequencygain parameter value) conductive by making connect_LF 52 HIGH in theperiods indicated by 55, i.e. periods, between a just-crossed period 53and a next zero crossing. In alternative embodiments, the just-crossedperiod 53 can also be taken longer than 1 bit, but one has to make surethat enough often the complimentary second switch 35 will be conductive,in order to keep the low-frequency gain parameter value, i.e. thevoltage on the LFgain node, updated. With just-crossed periods longerthan one bit, the first switch 34 can be driven to the conductive stateduring several bits on a row, as indicated by reference number 54 inFIG. 2, when having alternating HIGH and LOW data bits 57. This naturalextension of the just-crossed period 53 doesn't hinder the goodoperation of the equalizer 41. A good practice is to make the connect_LFsignal 52 HIGH at moments when the connect_HF signal 53 is LOW. However,it is also possible to wait a little time 56 after a falling edge of theconnect_HF signal 51, before making the connect_LF signal 52 HIGH e.g. atime with a fixed duration of the order of 1 bit or less, for example atime between one third of a bit and one bit, or thus for the 1-Gbpsexample given above between ⅓ ns and 1 ns. The falling edge of theconnect_LF signal and the rising edge of the connect_HF signal should bealigned close to a zero-crossing in the signal 50 at the output of theamplifying compensation stages for achieving reliable tuning of the gainparameters, e.g. LFgain and HFgain loops, e.g. by taking the latency ofthe detection mechanism 42, e.g. rectifying comparator circuit, intoaccount.

The HFgain and LFgain nodes are preferably capacitively coupled to theground, by means of a (parasitic) capacitor CHF and CLF, respectively,to average out the impulses given to them through the first and secondswitches 34, 35. In that way, they become the dominant pole in theHFgain and LFgain tuning loops. The first and second switches 34, 35 mayhave a large resistive value in their conductive state (e.g. by usingminimal area transistors), such that finding the optimal HFgain andLFgain values gets averaged out over more than 1 edge, e.g. 10 to 10000edges. The lower this number of edges, the quicker the self adaptiveequalizer 41 will converge to its final destination, however the more itcan become dependent on single-event signal errors. Since in mostapplications, the start-up speed is not an issue, it is advised to relyon a larger set of edges, in other words, to average out over a longerperiod.

An alternative to the proposed system, as shown hereinabove, is to workwith small currents that drive the voltages on the capacitors CHF andCLF upwards and/or downwards. The driving currents then have a durationdetermined by the duration of the just-crossed period 53, and have anamplitude dependent on the amplitude of the compensated signal at theoutput nodes preA, preB of the amplifying compensation stages.

FIG. 3 shows an example of an implementation of the connect block 33 ofthe updating circuit 40 for generating the connection signals connect_LFand connect_HF. Transistors M1, M2, M3, M13 and M14 can be considered asan input stage 20, amplifiying the differential signal at its inputsIN1, IN2 (which corresponds to the signal at the output nodes preA andpreB at the output of the compensation stages). Transistors M4, M5, M15,M16 and resistor R1 form a first output stage 21 that goes to HIGH onnode 25 during a certain input polarity of the input signal. TransistorsM6, M7, M17, M18 and resistor R2 form a second output stage 22 that goesto HIGH on node 26 during the opposite input polarity of the inputsignal. The outputs of these first and second output stages, the signalsone nodes 25 and 26, have short rise times, and long fall times. Thesefall times are long due to the use of resistors R1 and R2. TransistorsM8 . . . M11, M19 & M20 form a symmetric NAND port 23 with respect tothe output connect_LF and an AND port when referred to output connect_HFby use of an inverter 24. Just before zero crossing, one of the signalson 25 and 26 is digitally HIGH, and one is digitally LOW. Just after thezero crossing, they will both be digitally HIGH, since the rise time wasdesigned to be short. This is the start of the “just crossed period” 53.One of the signals on nodes 25 or 26 will then decrease relativelyslowly due to the resistor in the discharge path, the transistor gatesof the NAND port 23, acting as load capacitance. Unless anotherzero-crossing happens, the signal will drop enough digitally LOW to makethe NAND gate switch its output. The “just crossed period” 53 is thenover and period 55 starts. This “just-crossed period” 53 can take theduration of several bits, depending on the resistor values of resistorsR1 and R2, and their capacitive loads (gates of the NAND port 23).During the just-crossed period 53, the connect_HF signal will bedigitally HIGH, thereafter, it will be digitally LOW. Connect_LF is theopposite of this signal in this embodiment. Using opposite signals forConnect_LF and Connect_HF works fine for most applications. One canhowever choose to let the connect_LF to go digitally HIGH, somewhatlater than the connect_HF went digitally LOW as aforementioned. Thismainly speeds up convergence, but precision of convergence is notaffected very much.

FIG. 4 illustrates an alternative embodiment of a rectifying comparatorcircuit 42, in which the rectifiers and the comparator are provided in acombined way. It also shows how the comparison can be obtained in a waysuch that the common mode of the signals won't spoil the effectivecomparison. The signals on the nodes preA, preB and postA, postB, i.e.on the nodes before and after the limiting amplifier 47 are input to therectifying comparator circuit 42. Capacitors C1 . . . C4 and resistorsR1 . . . R4 form an AC-coupling system. The capacitors C1, C2, C3, C4are bypassing the input signals with essentially their full swing, andthe resistors R1, R2, R3, R4 bias the average voltages to the voltagepresent on voltage source V1. In other words, the differential voltagesoriginating from different places in the circuit (before and after thelimiting amplifier 47) are leveled to a voltage level V1. This voltageV1 is chosen to be in the common mode input range of the subsequentrectifying comparator. preA and preB are the signals that are also theinput voltages to the limiting amplifier. postA and postB are thesignals at the output of the limiting amplifier. The gates oftransistors M1 and M2 are driven by the level shifted preA and preBsignals. Whichever signal on the nodes preA, preB has highest voltage,its connected transistor M1, M2 will go into comparison, with the signalon any of the transistors M3 and M4. The gates of transistors M3 and M4are driven by the level shifted postA and postB signals. Whichever ofthese signals has highest voltage, its connected transistor will go intocomparison, with the signal on any of the transistors M1 and M2. In thisway, the highest signal of preA and preB will be compared to the highestsignal of postA and postB. When it is assumed that there is no timedependent common mode component on either of the signals, one can provethat one actually performs an action that is similar to comparing theabsolute value of the input of the limiting amplifier with the absolutevalue of the output of the limiting amplifier. This is also similar tofirst rectifying and then comparing the input signal with the outputsignal of the limiting amplifier.

Other detection circuits 42 providing similar merits can also bedesigned by a person skilled in the art, without departing from thescope of the invention as defined by the appended claims. However, thecombination of comparing the highest of the signals in a doubledifferential stage as in FIG. 4 is advised to be used. Mirroring throughtransistors M5 . . . M8 and generating an output signal that can spanthe full output voltage range is known by the person skilled in the art.Also other output structures than this can be used. The output out ofthe detection circuit 42, e.g. rectifying comparator circuit, delivers acomparison signal for use on node adjust_gain for controlling theadaptation of the gain in function of the compensated signal at theoutput of the amplifying compensation stages.

FIG. 5 shows curves illustrating the operation of the adaptive equalizer41. Curves 11, 12 are signals at nodes preA, preB at the input of thelimiting amplifier 47. Signals 13, 14 are signals at nodes postA, postBat the output of the limiting amplifier 47. Just after each transition18 (i.e. after a zero crossing 18), the curves 11 & 12 show overshootswith respect to curves 13 & 14. In other words, the amount of HF-gainhas to be decreased. Some time later, and until the next zero crossing,the amplitude between signals 11 and 12 is smaller than between signals13 and 14. So the low frequency gain LF-gain has to increase. Signal 15is the signal at node adjust_gain, being the output of the detectioncircuit 42, e.g. rectifying comparator circuit. Just after eachzero-crossing, this signal goes digitally LOW, indicating that the highfrequency gain HFgain should be decreased. Somewhat later, it goesdigitally HIGH indicating that the low frequency gain LFgain must beincreased.

Curve 16 is the connect_HF signal that shows when the switch 34 towardsthe HFgain node has to become conductive. Curve 17 is the connect_LFsignal that shows when the switch 35 towards the LFgain node has tobecome conductive. As it is shown, the “just crossed period 19” is notprecisely matching the periods when signal 15 on the node adjust_gain isdigitally LOW. This shows that there is some crosstalk between the twoerror detectors for the high frequency gain and the low frequency gain.In this case, the high frequency gain HFgain updating is not onlydetermined by the high frequency gain HFgain being too LOW, but also bythe low frequency gain LFgain being too HIGH. This is not a problem,since after some time the low frequency gain error will go to zero, andby then, the high frequency gain detector will be depending solely onthe its own high frequency gain error. The exact “just crossed period”length 19 is thus not so critical. It is suggested to be taken between0.3 and 3 bits period, in particular cases between 0.5 and 1 bitsperiod.

In general, this way of operating the detection for low frequency gainLFgain and high frequency gain HFgain updating is very robust withrespect to mismatches in transistor pairs. This is due to the fact thatthe gain adjustment signals are split into error signals for highfrequency gain and low frequency gain updating only late in theprocedure: in the embodiments illustrated, signals are first rectifiedand amplified in the rectifying comparator circuit 42, before splittingthem into error signals for the high frequency gain HFgain and lowfrequency gain LFgain updating. At the place the signals are split (atthe first and second switches 34, 35) the signals are very large withrespect to possible transistor offsets due to this prior amplification.Before the switches 34, 35, a mismatch, e.g. in the comparator 32, isnot harming the balance between the low frequency gain LFgain and thehigh frequency gain HFgain: such mismatch will only result in adifferent amplitude of the EYE diagram before and after the limitingamplifier 47: both low frequency LFgain and high frequency gain HFgainwill be tuned to a too HIGH or a too LOW value (depending on the sign ofthe offset mismatch), but low frequency gain LFgain and high frequencygain HFgain will be still in balance which each other.

An option is to make the “just crossed period” length 19 dependable onthe features in the high-speed data signal e.g. “preA-preB” at the levelof the input of the limiting amplifier 47. One can for example choose tomake the period length 19 adapt to the shortest measured HIGH or LOWperiods in this data signal. In that way a good equalizing precision canbe obtained over a large frequency (or bit-) range of operation. Anotheroption is to make the “just crossed period” length 19 dependable oninternal signal values, including on HFgain, LFgain or bitrate. In thelatter case, a sensor may be provided that measures the bit rate.Commercial broadband equalizers require that at lower bit rate alsolonger cable lengths can be equalized. One can thus anticipate that,when having high compensation levels (=a relative high high-frequencygain HFgain voltage), longer transmission cable is attached to the inputof the equalizer 41, and that a lower bit rate is to be handled. The“just crossed period” length 19 can then be increased accordingly.

At high speed, with respect to the used chip-technology, the detectioncircuit 42, e.g. the rectifying comparator like in FIG. 4, may not beable to generate enough gain to cover the whole range of voltagesrequired by nodes LFgain and HFgain. In that case the gain of thedetection circuit 42, e.g. the comparator gain of comparator 32, can bekept to a moderate value, e.g to a factor of 2-5, then the switching canbe performed, and then more gain can be applied (another factor of e.g.10-100), as is being illustrated in FIG. 6. In the embodimentillustrated in FIG. 6 first and second updating amplifiers 36, 37 areshown to demonstrate a good position of the extra gain stages 36, 37.The position of the updating amplifiers 36, 37 as illustrated in FIG. 6is particularly good, as in this embodiment the amplifiers 36, 37 may beslow amplifiers, which is not the case if the amplifiers 36, 37 arelocated before the split (node adjust_gain). Furthermore, a position ofthe amplifiers 36, 37 after the capacitors CHF, CLF is not good fornoise issues.

FIG. 7 shows an extension of the basic principle of the presentinvention to a third tuning parameter, the MFgain (middle frequencygain). Extensions to more tuning parameters are possible as well,although not explained in detail in the present document. The updatingcircuit 40 comprises a connect control block 33, and three switches 34,35, 38. The switches 34, 35, 38 are for linking through gain updatingsignals on the output node adjust_gain of the detection circuit 42 tothe respective gain nodes HFgain, LFgain, MFgain at appropriate momentsin time under control of the connect control block 33. The connectcontrol block 33 as in the embodiment explained with regard to FIG. 1and FIG. 6, generates a first signal connect_HF that is digitally HIGHjust after a cross-over period and a second signal connect_LF that isdigitally HIGH before a cross-over period. The connect control block 33now also generates a third signal connect_MF, that is digitally HIGH inbetween the period that connect_HF and connect_LF are digitally HIGH. Azero crossing still terminates the being HIGH of connect_LF, and stillstarts the going HIGH of connect_HF. In this way, a larger set ofdifferent types of cables can be compensated, since the matching of theamplification curve with the cable attenuation curve can be achieved atdifferent frequencies, corresponding to different moments in time,according to embodiments of the present invention. Further this can alsoserve the operation over an extended operational bit frequency in thedata signal.

FIG. 8 illustrates the positioning of the connect_MF in the middlebetween connect_HF and connect_LF, i.e. the middle frequency gain isadjusted after the high frequency gain has been adjusted and before thelow frequency gain is adjusted. Just after a zero crossing of the datasignal 60 at the output of the compensation stages, in particular at theoutput of the last compensation stage 46, connect_HF 61 goes digitallyHIGH, for a first period, e.g. a first fixed period, followed byconnect_MF 62 going digitally HIGH for a second period, e.g. a secondfixed period, followed by connect_LF 63 going digitally HIGH until thenext zero-crossing of the data signal 60. When a zero-crossing in datasignal 60 occurs in the middle of the period when connect_MF 62 isdigitally HIGH, connect_MF 62 should go digitally LOW as soon aspossible, and in that case connect_LF will not go digitally HIGH untilthe next opportunity to do so, i.e. until after the next time connect_MFhas gone digitally HIGH and digitally LOW again. When a zero-crossing indata signal 60 occurs in the middle of the period when connect_LF 63 isdigitally HIGH, connect_LF 63 should go digitally LOW as soon aspossible. A person skilled in the art can design a control circuit 33that accordingly generates these sampling signals connect_HF 61,connect_MF 62 and connect_LF 63 in function of the compensate datasignal 60 on the output nodes preA, preB of the amplifying compensationstages.

Analogously to what is explained with respect to FIG. 2, connect_MF cango digitally HIGH as soon as connect_HF is digitally LOW, and connect_LFcan go digitally HIGH as soon as connect_MF is digitally LOW.Alternatively, it is possible to wait a little time, e.g. in the orderof one third to 1 bit, after a falling edge of connect_HF, respectivelyconnect_MF before making connect_MF, respectively connect_LF digitallyHIGH. It is particularly advantageous to align the falling edge ofconnect_LF and the rising edge of connect_HF close to the zero-crossingin data signal 60 for achieving reliable tuning of the gain loops.

For some less demanding applications, it can be sufficient to provide alimited number of switches in the updating mechanism 40, the limitednumber of switches being less than the number of gain parameters used inthe compensation stages. As an example only, an equalizer 41 isillustrated in FIG. 9, having a cascade of four amplifying compensationstages 43, 44, 45, 46, each of the amplifying compensation stages havingat least one gain parameter, for example, as illustrated in FIG. 9, onegain parameter LFgain that tunes the low frequency gain, and anothergain parameter HFgain that tunes the high frequency gain. The at leastone gain parameter is changed, in accordance with embodiments of thepresent invention, in function of the compensated signal at the outputnodes preA, preB of the last compensation stage 46. If this compensatedsignal is too high, the gain parameters will be lowered, and if thecompensated signal is too low, the gain parameters will be raisedcorrespondingly. In order to determine the change of the gainparameters, a detection mechanism 42 for determining the required highfrequency gain and low frequency gain is provided, as also explainedwith regard to other embodiments described. The control of the gainparameters is performed in updating mechanism 40 as explainedhereinafter.

In the update mechanism 40 a limited number of switches, the numberbeing smaller than the number of gain parameters used in the amplifyingcompensation stage, e.g. only one switch 39, may be present, as forexample illustrated in FIG. 9, where the switch 39 is provided at theupdating side for the HFgain parameter. The LFgain parameter is thenupdated by the full average of the adjust_gain signal, including theerror signal used for the HFgain updating. During a pre-determinedperiod after a zero-crossing of the data, e.g. on the node preA, preB,the signal on the output node adjust_gain of the detection circuit 42,in the embodiment illustrated in FIG. 9 the output of comparator 32, isindicative for whether there is too much or too little high frequencygain. The updating circuit 40 comprises a connect control block 33, tocontrol the enable of switch 39 to link through the signal on the outputnode adjust_gain of the comparator 32 to the HFgain node. At the sametime, the signal on the output node adjust_gain of the comparator 32 isalso linked through to the LFgain node. The HFgain voltage (gainparameter) is adapted in the right direction (up or down, depending onthe signal adjust_gain), and the LFgain voltage (gain parameter) isadapted in the same direction. By the time, however, that the HFgaingets at its correct value, switch 39 will be controlled by connectcontrol block 33 to switch off, an the signal adjust_gain will thensolely serve to bring the LFgain at its best position as well. It is,however, advised to use a system whereby the plurality of gainparameters, preferably all gain parameters, are each getting updatedthrough switches as in the previous embodiments.

It is to be understood that although preferred embodiments, specificconstructions and configurations, as well as materials, have beendiscussed herein for devices according to the present invention, variouschanges or modifications in form and detail may be made withoutdeparting from the scope and spirit of this invention.

1-33. (canceled)
 34. An equalizer filter for compensating a receiveddistorted data signal for frequency dependent signal modificationsintroduced by a transmission channel, said equalizer filter comprisingat least one compensation stage (Xstage1, Xstage2, Xstage3, Xstage4), acompensation stage (Xstage1, Xstage2, Xstage3, Xstage4) having at leastone gain parameter (LFgain, HFgain), the equalizer filter comprising atleast one switch, the at least one switch being for changing the atleast one gain parameter (LFgain, HFgain) in time in function of thecompensated signal, connect signals (connect_LF and connect_HF)controlling the at least one switch for changing the at least one gainparameter (HFgain and Lfgain) in response to zero-crossings of the datasignal.
 35. The equalizer filter according to claim 34, comprising acontrol circuit for controlling the actuation of the at least one switchso as to control when the at least one gain parameter (LFgain, HFgain)is changed.
 36. The equalizer filter according to claim 34, comprisingstorage means for storing the gain parameters (LFgain, Hfgain).
 37. Theequalizer filter according to claim 34, comprising a detection circuitfor detecting from the compensated signal mismatches in gain parameters(HFgain, LFgain), and for generating a corresponding mismatch detectionsignal.
 38. The equalizer filter according to claim 37, wherein themismatch detection signal instantaneously indicates a required increaseor decrease of the gain parameters (HFgain, LFgain).
 39. The equalizerfilter according to claim 34, wherein the at least one switch is adaptedto signal through the mismatch detection signal, thus updating at leastone of the gain parameters (LFgain, HFgain) with the required increaseor decrease.
 40. The equalizer filter according to claim 34, wherein thedetection circuit comprises a rectifying comparator circuit.
 41. Theequalizer filter according to claim 37, wherein the detection circuitcomprises two differential inputs (preA, preB; postA, postB).
 42. Theequalizer filter according to claim 41, each differential inputcomprising two input nodes, wherein the detection circuit is adapted tocompare, from each differential input, signals on those input nodeswhich are highest in voltage.
 43. The equalizer filter according toclaim 37, wherein the detection circuit comprises a comparator.
 44. Theequalizer filter according to claim 37, wherein the detection circuit isadapted for comparing input and output signals of a limiting amplifier.45. The equalizer filter according to claim 37, wherein the detectioncircuit comprises at least one rectifier.
 46. An equalizer filter forcompensating a received distorted signal for frequency dependent signalmodifications introduced by a transmission channel, said equalizerfilter comprising: at least one compensation stage (Xstage1, Xstage2,Xstage3, Xstage4), there being at least two gain parameters (LFgain,HFgain) for the compensation stages, each compensation stage (Xstage1,Xstage2, Xstage3, Xstage4) having at least one gain parameter, a gainparameter updating circuit for updating the at least two gainparameters, and a detection circuit for detecting, from the compensatedsignal, mismatches in the gain parameters (HFgain, LFgain), wherein thedetection circuit is adapted for generating a mismatch detection signal,the mismatch detection signal being common for the at least two gainparameters, a time domain between two zero-crossings of the data signalat output nodes of the at least one compensation stage being split intodifferent parts, each part being for updating a particular gainparameter.
 47. The equalizer filter according to claim 46, wherein themismatch detection signal instantaneously indicates a required increaseor decrease of the gain parameters (HFgain, LFgain).
 48. The equalizerfilter according to claim 46, wherein the detection circuit comprisestwo differential inputs (preA, preB; postA, posts).
 49. The equalizerfilter according to claim 48, each differential input comprising twoinput nodes, wherein the detection circuit is adapted to compare, fromeach differential input, signals on those input nodes which are highestin voltage.
 50. The equalizer filter according to claim 48, wherein thedetection circuit comprises at least one rectifier for rectifyingsignals on the differential inputs.
 51. The equalizer filter accordingto claim 46, wherein the detection circuit comprises a comparator forcomparing signals on the differential inputs.
 52. The equalizer filteraccording to claim 46, wherein the detection circuit is adapted forcomparing input and output signals of a limiting amplifier.
 53. Theequalizer filter according to claim 46, furthermore comprising at leastone switch, the at least one switch being for changing at least one ofthe gain parameters (LFgain, HFgain) in time in function of thecompensated signal.
 54. The equalizer filter according to claim 53,wherein the at least one switch is adapted to signal through themismatch detection signal for updating the at least one gain parameter(LFgain, HFgain) with the required increase or decrease.
 55. Anequalizer system for compensating a received distorted signal forfrequency dependent signal modifications introduced by a transmissionchannel, said equalizer system comprising an equalizer filter accordingto claim
 34. 56. A method for compensating a distorted signal forfrequency dependent signal modifications introduced by a transmissionchannel, the signal having an amplitude, the method comprising receivinga distorted data signal, providing at least two gain parameters (LFgain,HFgain) and compensating said distorted data signal by amplifying thereceived signal in at least one amplifying compensation stage using theprovided gain parameters, outputting a compensated signal, the methodfurthermore comprising as a function of the amplitude of the compensatedsignal (preA-preB), changing at least one of the gain parameters(LFgain, HFgain) multiplexed in time, a time domain between twozero-crossings of the data signal at output nodes of the at least onecompensation stage being split into different parts, each part being forupdating a particular gain parameter.
 57. The method according to claim56, wherein the step of changing the gain parameters comprisesgenerating a mismatch detection signal from the compensated signal andmultiplexing that mismatch detection signal in time for adapting atleast one of the gain parameters.
 58. The method according to claim 57,wherein the mismatch detection signal instantaneously indicates arequired increase or decrease of at least one of the gain parameters.59. The method according to claim 57, wherein the step of generating amismatch detection signal comprises comparing the compensated signalwith an amplified and/or saturated version of the compensated signal.60. The A method according to claim 57, comprising using the mismatchdetection signal for changing at least one of the gain parameters. 61.The method according to claim 60, wherein the step of changing the gainparameters comprises multiplexing at least one switch in time, formultiplexed signalling through the mismatch detection signal to at leastone of the gain parameters.
 62. The method according to claim 56,comprising storing the at least two gain parameters.
 63. A method forcompensating a distorted data signal for frequency dependent signalmodifications introduced by a transmission channel, the signal having anamplitude, the method comprising receiving a data distorted signal,providing at least two gain parameters (LFgain, HFgain) and compensatingsaid distorted data signal by amplifying the received signal in at leastone amplifying compensation stage using the provided gain parameters,outputting a compensated signal, detecting, from the compensated datasignal, mismatches in the gain parameters and updating the at least twogain parameters, wherein detecting mismatches in the gain parameters isadapted for generating a mismatch detection signal common for the atleast two gain parameters, a time domain between two zero-crossings ofthe data signal being split into different parts, each part being forupdating a particular gain parameter.
 64. The method according to claim63, wherein updating the at least two gain parameters comprisesmultiplexing in time the common detection signal between each of the atleast two gain parameters, so as to change the gain parameters (LFgain,HFgain) in time as a function of the compensated signal.
 65. The methodaccording to claim 63, wherein the mismatch detection signalinstantaneously indicates a required increase or decrease of at leastone of the gain parameters (HFgain, LFgain).
 66. The method according toclaim 65, wherein updating the at least two gain parameters comprisessignalling through the mismatch detection signal for updating the gainparameters (LFgain, HFgain) with the required increase or decrease.